1. Field of the Invention
The present invention relates to a control circuit for power devices such as IGBTs.
2. Description of the Background Art
FIG. 17 is a circuit diagram of a conventional control circuit for power devices of half-bridge connection. Referring to FIG. 17, transistors Q1 and Q2 which are power devices such as IGBTs are connected between main power sources P and N in the form of a totem-pole, and flywheel diodes D1 and D2 are connected in antiparallel to the transistors Q1 and Q2, respectively. An inductive load 1 is connected to a connecting point U of the emitter of the transistor Q1 and the collector of the transistor Q2.
The transistors Q1 and Q2 are driven and controlled on different control voltages VH and VL, respectively. The control voltage VL based on the emitter potential (ground level) of the transistor Q2 is supplied from the positive electrode of a power supply VLS having a grounded negative electrode.
The control voltage VH based on the emitter potential of the transistor Q1 is supplied from the positive electrode of a capacitor CP having a negative electrode connected to the emitter of the transistor Q1. The positive electrode of the capacitor CP is connected to the cathode of a diode DP, and the negative electrode thereof is connected to the emitter of the transistor Q1. The electrical charge charged from the power supply VLS to the capacitor CP through the diode DP is used as the control voltage VH.
The anode of the diode DP is connected to the positive electrode of the power supply VLS. In the drawings, the symbol .gradient. indicates connection to the emitter of the transistor Q1.
The control voltage VH for driving the upper transistor Q1 and the control voltage VL for driving the lower transistor Q2 are supplied by means of the single power supply VLS.
An input signal V.sub.IN 1 is accepted by an edge trigger pulse generating circuit P1, and an input signal V.sub.IN 2 is accepted by a controller 2. The input signals V.sub.IN 1 and V.sub.IN 2 are based on the control voltage VL.
The edge trigger pulse generating circuit PG1, in response to the input signal V.sub.IN 1, outputs turn-on pulses to a level shifting circuit L.sub.ON for turn-on operation at such time intervals as to turn on the transistor Q1 (H level rising timings of the input signal V.sub.IN 1), and also outputs turn-off pulses to a level shifting circuit L.sub.OFF for turn-off operation at such time intervals as to turn off the transistor Q1 (L level falling timings of the input signal V.sub.IN 1).
The level shifting circuit L.sub.ON level-shifts the turn-on pulses based on the control voltage VL into a signal based on the control voltage VH to output the signal to a set input S1 of a flip-flop FF1. Likewise, the level shifting circuit L.sub.OFF shifts the level of the turn-off pulses based on the control voltage VL into a signal based on the control voltage VH to output the signal to a first input of an OR gate G1.
A control power supply voltage drop protecting circuit UV1 monitors the control voltage VH to output a control voltage drop detection signal SM to a second input of the OR gate G1, the control voltage drop detection signal SM being H when the control voltage VH decreases abnormally and being L in other cases.
A current sensor CS1 converts a current flowing in a sense electrode of the transistor Q1 and outputs a sense voltage VS, which is applied to the positive input of an overcurrent protecting circuit OC1 including a comparator. The overcurrent protecting circuit OC1 has a negative input receiving a reference voltage VR and outputs an overcurrent detection signal SO to a third input of the OR gate G1.
The flip-flop FF1 has a reset input R1 receiving the output of the OR gate G1 and a Q-output Q01 connected to the input of a driver DR1. The output of the driver DR1 is applied to the gate of the transistor Q1.
An output voltage detecting circuit VM is also connected to the connecting point U. The output voltage detecting circuit VM monitors and compares a voltage VU at the connecting point U with a predetermined potential to output a potential comparison signal SC of "H"/"L" level to an abnormality detecting circuit FS.
The abnormality detecting circuit FS receives the potential comparison signal SC and the input signal V.sub.IN 1 to output an abnormality signal FO indicating whether or not the transistor Q1 is abnormal in response to the received signals.
The controller 2 performs the drive-control such as on-off control of the transistor Q2 in response to the input signal V.sub.IN 2. A portion 31 enclosed by the dotted line of FIG. 17 is the control circuit for power devices (transistors Q1 and Q2).
In such an arrangement, when the input signal V.sub.IN 1 indicates turn-on, the control voltage VH level "H" is applied to the set input S1 of the flip-flop FF1 through the edge trigger pulse generating circuit P1 and level shifting circuit L.sub.ON.
As a result, the Q-output Q01 of the flip-flop FF1 goes high, which is applied to the gate of the transistor Q1 through the driver DR1. The transistor Q1 then enters the on-state.
On the other hand, when the input signal V.sub.IN 1 indicates turn-off, the control voltage VH level "H" is applied to the reset input R1 of the flip-flop FF1 through the edge trigger pulse generating circuit PG1, level shifting circuit L.sub.OFF and OR gate G1.
As a result, the Q-output Q01 of the flip-flop FF1 goes low, which is applied to the gate of the transistor Q1 through the driver DR1. The transistor Q1 then enters the off-state.
When the transistor Q1 is in an overcurrent supply state and the sense voltage VS exceeds the reference voltage VR, the overcurrent detection signal SO of the overcurrent protecting circuit OC1 goes high, which is applied to the reset input R1 of the flip-flop FF1 through the OR gate G1.
As a result, the Q-output Q01 of the flip-flop FF1 goes low, which is applied to the gate of the transistor Q1 through the driver DR1. The transistor then enters the off-state and is released from the overcurrent supply state.
When the control voltage VH decreases abnormally, the control voltage drop detection signal SM goes high, which is applied to the reset input R1 of the flip-flop FF1 through the OR gate G1.
As a result, the Q-output Q01 of the flip-flop FF1 goes low, which is applied to the gate of the transistor Q1 through the driver DR1. The transistor then enters the off-state. The charging of the capacitor CP restarts, and the control voltage VH returns to the normal level.
In the off-state of the transistor Q1, the voltage VU at the connecting point U decreases. When the voltage VU decreases to a level lower than the predetermined potential of the output voltage detecting circuit VM, the potential comparison signal SC changes to "L". If the input signal V.sub.IN 1 indicates the on-state at that time, the abnormality detecting circuit FS judges that the overcurrent supply state of the transistor Q1 or the abnormal decrease in control voltage VH has forced the transistor Q1 to turn off and outputs the abnormality signal FO indicative of abnormalities.
FIG. 18 shows the control circuit for power devices of FIG. 17 which drives a three-phase motor. Referring to FIG. 18, the transistors Q1, Q2 which are power devices, transistors Q3, Q4, and transistors Q5, Q6 are totem-pole connected to each other, and are three-phase bridge connected between the power sources P and N. Inputs of a motor M are connected to connecting points U, V, W of the transistors, respectively.
Flywheel diodes D1 to D6 are connected in antiparallel to the transistors Q1 to Q6, respectively. Outputs of control circuits 31 to 33 for performing controls such as drive or protection of IGBTs are applied to the gates of the transistors Q1 to Q6.
The control circuits 31 to 33 turn on and off the transistors Q1 to Q6 in response to control signals S10 to S30 from a controller 40 including a microcomputer or the like and controls the operation of the motor M.
The elements of FIG. 18 are in the following relation with those of FIG. 17. The elements Q1, Q2, D1, D2 and the control circuit 31 of FIG. 18 are equivalent to those of FIG. 17. The motor M of FIG. 18 is equivalent to the inductive load 1 of FIG. 17. The control signal S10 of FIG. 18 is equivalent to the input signals V.sub.IN 1 and V.sub.2 2 of FIG. 17. It is a common practice to integrate the control circuits 31 to 33.
The conventional control circuit for power devices of half-bridge connection having the above-mentioned arrangement has detected the abnormalities of the power devices by monitoring the potential VU at the connecting point U. This presents the problem that it is impossible to determine whether the abnormality indicated by the abnormality signal FO results from the overcurrent supply state of the transistor Q1 or the abnormal decrease of the control voltage VH.
The capacitor CP supplies the control voltage VH of the transistor Q1. During the time the transistor Q1 is on and the potential VU at the connecting point U is high, the capacitor CP discharges, causing the control voltage VH to decrease with time.
Thus, a need has arisen to limit the rated current capacity and maximum on-time of the transistor Q1. This limitation is also disadvantageous in that the input signal V.sub.IN 1 must be set so that the capacitor CP is periodically charged in consideration for the decreasing control voltage VH.